2 Description of the MIPS R2000
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Figure 2: MIPS R2000 CPU and FPU
A MIPS processor consists of an integer processing unit (the CPU) and
a collection of coprocessors that perform ancillary tasks or operate
on other types of data such as floating point numbers (see
Figure 2). SPIM simulates two coprocessors. Coprocessor
0 handles traps, exceptions, and the virtual memory system. SPIM
simulates most of the first two and entirely omits details of the
memory system. Coprocessor 1 is the floating point unit. SPIM
simulates most aspects of this unit.
Table: MIPS registers and the convention governing their use.
The MIPS (and SPIM) central processing unit contains 32 general
purpose registers that are numbered 0-31. Register 
is designated
by $n. Register $0 always contains the hardwired value
0. MIPS has established a set of conventions as to how registers
should be used. These suggestions are guidelines, which are not
enforced by the hardware. However a program that violates them will
not work properly with other software. Table 2 lists the
registers and describes their intended use.
Registers $at (1), $k0 (26), and $k1 (27) are
reserved for use by the assembler and operating system.
Registers $a0-$a3 (4-7) are used to pass the first
four arguments to routines (remaining arguments are passed on the
stack). Registers $v0 and $v1 (2, 3) are used to return
values from functions. Registers $t0-$t9 (8-15, 24,
25) are caller-saved registers used for temporary quantities that do
not need to be preserved across calls. Registers $s0-$s7 (16-23) are callee-saved registers that hold long-lived values
that should be preserved across calls.
Register $sp (29) is the stack pointer, which points to the
first free location on the stack. Register $fp (30) is the
frame pointer.[+] Register $ra (31) is written with the return address
for a call by the jal instruction.
Register $gp (28) is a global pointer that points into the
middle of a 64K block of memory in the heap that holds constants and
global variables. The objects in this heap can be quickly accessed
with a single load or store instruction.
In addition, coprocessor 0 contains registers that are useful to
handle exceptions. SPIM does not implement all of these registers,
since they are not of much use in a simulator or are part of the
memory system, which is not implemented. However, it does provide the
following:
These registers are part of coprocessor 0's register set and are
accessed by the lwc0, mfc0, mtc0, and swc0
instructions.
Figure: The Status register.
Figure: The Cause register.
Figure 3 describes the bits in the Status
register that are implemented by SPIM. The interrupt mask
contains a bit for each of the five interrupt levels. If a bit is
one, interrupts at that level are allowed. If the bit is zero,
interrupts at that level are disabled. The low six bits of the Status register implement a three-level stack for the kernel/user and interrupt enable bits. The kernel/user
bit is 0 if the program was running in the kernel when the interrupt
occurred and 1 if it was in user mode. If the interrupt enable
bit is 1, interrupts are allowed. If it is 0, they are disabled. At an
interrupt, these six bits are shifted left by two bits, so the current
bits become the previous bits and the previous bits become the old
bits. The current bits are both set to 0 (i.e., kernel mode with
interrupts disabled).
Figure 4 describes the bits in the Cause
registers. The five pending interrupt bits correspond to the
five interrupt levels. A bit becomes 1 when an interrupt at its level
has occurred but has not been serviced. The exception code
register contains a code from the following table describing the cause
of an exception.
Processors can number the bytes within a word to make the byte with
the lowest number either the leftmost or rightmost one. The convention
used by a machine is its byte order. MIPS processors can
operate with either big-endian byte order:
or little-endian byte order:
SPIM operates with both byte orders. SPIM's byte order is determined
by the byte order of the underlying hardware running the simulator.
On a DECstation 3100, SPIM is little-endian, while on a HP Bobcat, Sun
4 or PC/RT, SPIM is big-endian.
MIPS is a load/store architecture, which means that only load and
store instructions access memory. Computation instructions operate
only on values in registers. The bare machine provides only one
memory addressing mode: c(rx), which uses the sum of the
immediate (integer) c and the contents of register rx as
the address. The virtual machine provides the following addressing
modes for load and store instructions:
Most load and store instructions operate only on aligned data. A
quantity is aligned if its memory address is a multiple of its
size in bytes. Therefore, a halfword object must be stored at even
addresses and a full word object must be stored at addresses that are
a multiple of 4. However, MIPS provides some instructions for
manipulating unaligned data.
In all instructions below, Src2 can either be a register or an
immediate value (a 16 bit integer). The immediate forms of the
instructions are only included for reference. The assembler will
translate the more general form of an instruction (e.g., add)
into the immediate form (e.g., addi) if the second argument is
constant.
- abs Rdest, Rsrc
-
Absolute Value
-
Put the absolute value of the integer from register Rsrc in
register Rdest.
-
add Rdest, Rsrc1, Src2
-
Addition (with overflow)
-
addi Rdest, Rsrc1, Imm
-
Addition Immediate (with overflow)
-
addu Rdest, Rsrc1, Src2
- Addition (without overflow)
-
addiu Rdest, Rsrc1, Imm
-
Addition Immediate (without overflow)
-
Put the sum of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.
-
and Rdest, Rsrc1, Src2
- AND
-
andi Rdest, Rsrc1, Imm
- AND Immediate
- Put the logical AND of the integers from register Rsrc1 and
Src2 (or Imm) into register Rdest.
-
div Rsrc1, Rsrc2
- Divide (signed)
-
divu Rsrc1, Rsrc2
- Divide (unsigned)
- Divide the contents of the two registers.
divu treats its operands as unsigned values. Leave the quotient in
register lo and the remainder in register hi. Note that
if an operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on which SPIM is
run.
-
div Rdest, Rsrc1, Src2
- Divide (signed, with overflow)
-
divu Rdest, Rsrc1, Src2
- Divide (unsigned, without overflow)
-
Put the quotient of the integers from register Rsrc1 and Src2 into register Rdest. divu treats its operands as unsigned
values.
-
mul Rdest, Rsrc1, Src2
- Multiply (without overflow)
-
mulo Rdest, Rsrc1, Src2
- Multiply (with overflow)
-
mulou Rdest, Rsrc1, Src2
- Unsigned Multiply (with overflow)
-
Put the product of the integers from register Rsrc1 and Src2 into register Rdest.
-
mult Rsrc1, Rsrc2
- Multiply
-
multu Rsrc1, Rsrc2
- Unsigned Multiply
-
Multiply the contents of the two registers. Leave the low-order word
of the product in register lo and the high-word in register hi.
-
neg Rdest, Rsrc
- Negate Value (with overflow)
-
negu Rdest, Rsrc
- Negate Value (without overflow)
-
Put the negative of the integer from register Rsrc into
register Rdest.
-
nor Rdest, Rsrc1, Src2
- NOR
-
Put the logical NOR of the integers from register Rsrc1 and
Src2 into register Rdest.
-
not Rdest, Rsrc
-
NOT
-
Put the bitwise logical negation of the integer from register Rsrc into register Rdest.
-
or Rdest, Rsrc1, Src2
- OR
-
ori Rdest, Rsrc1, Imm
- OR Immediate
-
Put the logical OR of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.
-
rem Rdest, Rsrc1, Src2
- Remainder
-
remu Rdest, Rsrc1, Src2
- Unsigned Remainder
-
Put the remainder from dividing the integer in register Rsrc1 by
the integer in Src2 into register Rdest. Note that if an
operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on which
SPIM is run.
-
rol Rdest, Rsrc1, Src2
- Rotate Left
-
ror Rdest, Rsrc1, Src2
- Rotate Right
- Rotate the contents of register Rsrc1 left (right) by the
distance indicated by Src2 and put the result in register
Rdest.
-
sll Rdest, Rsrc1, Src2
- Shift Left Logical
-
sllv Rdest, Rsrc1, Rsrc2
- Shift Left Logical Variable
-
sra Rdest, Rsrc1, Src2
- Shift Right Arithmetic
-
srav Rdest, Rsrc1, Rsrc2
- Shift Right Arithmetic Variable
-
srl Rdest, Rsrc1, Src2
- Shift Right Logical
-
srlv Rdest, Rsrc1, Rsrc2
- Shift Right Logical Variable
- Shift the contents of register Rsrc1 left (right) by the
distance indicated by Src2 (Rsrc2) and put the
result in register Rdest.
-
sub Rdest, Rsrc1, Src2
- Subtract (with overflow)
-
subu Rdest, Rsrc1, Src2
- Subtract (without overflow)
- Put the difference of the integers from register Rsrc1 and Src2 into register Rdest.
-
xor Rdest, Rsrc1, Src2
- XOR
-
xori Rdest, Rsrc1, Imm
- XOR Immediate
- Put the logical XOR of the integers from register Rsrc1 and
Src2 (or Imm) into register Rdest.
-
li Rdest, imm
- Load Immediate
- Move the immediate imm into register Rdest.
-
lui Rdest, imm
- Load Upper Immediate
- Load the lower halfword of the immediate imm into the upper
halfword of register Rdest. The lower bits of the register are
set to 0.
In all instructions below, Src2 can either be a register or an
immediate value (a 16 bit integer).
- seq Rdest, Rsrc1, Src2
- Set Equal
- Set register Rdest to 1 if register Rsrc1 equals Src2 and to be 0 otherwise.
-
sge Rdest, Rsrc1, Src2
- Set Greater Than Equal
- sgeu Rdest, Rsrc1, Src2
- Set Greater Than Equal Unsigned
- Set register Rdest to 1 if register Rsrc1 is greater
than or equal to Src2 and to 0 otherwise.
- sgt Rdest, Rsrc1, Src2
- Set Greater Than
-
sgtu Rdest, Rsrc1, Src2
- Set Greater Than Unsigned
- Set register Rdest to 1 if register Rsrc1 is greater
than Src2 and to 0 otherwise.
- sle Rdest, Rsrc1, Src2
- Set Less Than Equal
- sleu Rdest, Rsrc1, Src2
- Set Less Than Equal Unsigned
- Set register Rdest to 1 if register Rsrc1 is less than
or equal to Src2 and to 0 otherwise.
-
slt Rdest, Rsrc1, Src2
- Set Less Than
-
slti Rdest, Rsrc1, Imm
- Set Less Than Immediate
-
sltu Rdest, Rsrc1, Src2
- Set Less Than Unsigned
-
sltiu Rdest, Rsrc1, Imm
- Set Less Than Unsigned Immediate
- Set register Rdest to 1 if register Rsrc1 is less than
Src2 (or Imm) and to 0 otherwise.
-
sne Rdest, Rsrc1, Src2- Set Not Equal
- Set register Rdest to 1 if register Rsrc1 is not equal
to Src2 and to 0 otherwise.
In all instructions below, Src2 can either be a register or an
immediate value (integer). Branch instructions use a signed 16-bit
offset field; hence they can jump 
instructions (not
bytes) forward or 
instructions backwards. The jump
instruction contains a 26 bit address field.
- b label
- Branch instruction
- Unconditionally branch to the instruction at the label.
-
bczt label
- Branch Coprocessor
True
-
bczf label
- Branch Coprocessor False
- Conditionally branch to the instruction at the label if coprocessor
's condition flag is true (false).
-
beq Rsrc1, Src2, label
- Branch on Equal
- Conditionally branch to the instruction at the label if the contents
of register Rsrc1 equals Src2.
-
beqz Rsrc, label
- Branch on Equal Zero
- Conditionally branch to the instruction at the label if the contents
of Rsrc equals 0.
-
bge Rsrc1, Src2, label
- Branch on Greater Than Equal
-
bgeu Rsrc1, Src2, label
- Branch on GTE Unsigned
- Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are greater than or equal to Src2.
-
bgez Rsrc, label
- Branch on Greater Than Equal Zero
- Conditionally branch to the instruction at the label if the contents
of Rsrc are greater than or equal to 0.
-
bgezal Rsrc, label
- Branch on Greater Than Equal Zero And Link
- Conditionally branch to the instruction at the label if the contents
of Rsrc are greater than or equal to 0. Save the address of
the next instruction in register 31.
-
bgt Rsrc1, Src2, label
- Branch on Greater Than
-
bgtu Rsrc1, Src2, label
- Branch on Greater Than Unsigned
- Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are greater than Src2.
-
bgtz Rsrc, label
- Branch on Greater Than Zero
- Conditionally branch to the instruction at the label if the contents
of Rsrc are greater than 0.
-
ble Rsrc1, Src2, label
- Branch on Less Than Equal
-
bleu Rsrc1, Src2, label
- Branch on LTE Unsigned
- Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are less than or equal to Src2.
-
blez Rsrc, label
- Branch on Less Than Equal Zero
- Conditionally branch to the instruction at the label if the contents
of Rsrc are less than or equal to 0.
-
bgezal Rsrc, label
- Branch on Greater Than Equal Zero And Link
-
bltzal Rsrc, label
- Branch on Less Than And Link
- Conditionally branch to the instruction at the label if the contents
of Rsrc are greater or equal to 0 or less than 0,
respectively. Save the address of the next instruction in register 31.
-
blt Rsrc1, Src2, label
- Branch on Less Than
-
bltu Rsrc1, Src2, label
- Branch on Less Than Unsigned
- Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are less than Src2.
-
bltz Rsrc, label
- Branch on Less Than Zero
- Conditionally branch to the instruction at the label if the contents
of Rsrc are less than 0.
-
bne Rsrc1, Src2, label
- Branch on Not Equal
- Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are not equal to Src2.
-
bnez Rsrc, label
- Branch on Not Equal Zero
- Conditionally branch to the instruction at the label if the contents
of Rsrc are not equal to 0.
-
j label
- Jump
- Unconditionally jump to the instruction at the label.
-
jal label
- Jump and Link
- jalr Rsrc
- Jump and Link Register
- Unconditionally jump to the instruction at the label or whose address
is in register Rsrc. Save the address of the next
instruction in register 31.
-
jr Rsrc- Jump Register
- Unconditionally jump to the instruction whose address is in register
Rsrc.
- la Rdest, address
- Load Address
- Load computed address, not the contents of the location, into
register Rdest.
-
lb Rdest, address
- Load Byte
-
lbu Rdest, address
- Load Unsigned Byte
- Load the byte at address into register Rdest. The byte
is sign-extended by the lb, but not the lbu, instruction.
- ld Rdest, address
- Load Double-Word
- Load the 64-bit quantity at address into registers Rdest
and Rdest + 1.
- lh Rdest, address
- Load Halfword
- lhu Rdest, address
- Load Unsigned Halfword
- Load the 16-bit quantity (halfword) at address into register
Rdest. The halfword is sign-extended by the lh, but not
the lhu, instruction
-
lw Rdest, address- Load Word
- Load the 32-bit quantity (word) at address into register Rdest.
- lwcz Rdest, address
- Load Word Coprocessor
- Load the word at address into register Rdest of
coprocessor (0-3).
-
lwl Rdest, address
- Load Word Left
-
lwr Rdest, address
- Load Word Right
- Load the left (right) bytes from the word at the possibly-unaligned
address into register Rdest.
- ulh Rdest, address
- Unaligned Load Halfword
-
ulhu Rdest, address
- Unaligned Load Halfword Unsigned
- Load the 16-bit quantity (halfword) at the possibly-unaligned address into register Rdest. The halfword is sign-extended
by the ulh, but not the ulhu, instruction
- ulw Rdest, address
- Unaligned Load Word
- Load the 32-bit quantity (word) at the possibly-unaligned address into register Rdest.
- sb Rsrc, address
- Store Byte
- Store the low byte from register Rsrc at address.
- sd Rsrc, address
- Store Double-Word
- Store the 64-bit quantity in registers Rsrc and Rsrc
+ 1 at address.
- sh Rsrc, address
- Store Halfword
- Store the low halfword from register Rsrc at address.
- sw Rsrc, address
- Store Word
- Store the word from register Rsrc at address.
- swcz Rsrc, address
- Store Word Coprocessor
- Store the word from register Rsrc of coprocessor at
address.
- swl Rsrc, address
- Store Word Left
swr Rsrc, address- Store Word Right
- Store the left (right) bytes from register Rsrc at the
possibly-unaligned address.
- ush Rsrc, address
- Unaligned Store Halfword
- Store the low halfword from register Rsrc at the
possibly-unaligned address.
- usw Rsrc, address
- Unaligned Store Word
- Store the word from register Rsrc at the possibly-unaligned
address.
- move Rdest, Rsrc
- Move
- Move the contents of Rsrc to Rdest.
The multiply and divide unit produces its result in two additional
registers, hi and lo. These instructions move values to and from
these registers. The multiply, divide, and remainder instructions
described above are pseudoinstructions that make it appear as if this
unit operates on the general registers and detect error conditions
such as divide by zero or overflow.
- mfhi Rdest
- Move From hi
- mflo Rdest
- Move From lo
- Move the contents of the hi (lo) register to register Rdest.
- mthi Rdest
- Move To hi
- mtlo Rdest
- Move To lo
- Move the contents register Rdest to the hi (lo) register.
Coprocessors have their own register sets. These instructions move
values between these registers and the CPU's registers.
- mfcz Rdest, CPsrc
- Move From Coprocessor
- Move the contents of coprocessor 's register CPsrc to CPU
register Rdest.
- mfc1.d Rdest, FRsrc1
- Move Double From Coprocessor 1
- Move the contents of floating point registers FRsrc1 and
FRsrc1 + 1 to CPU registers Rdest and Rdest + 1.
- mtcz Rsrc, CPdest
- Move To Coprocessor
- Move the contents of CPU register Rsrc to coprocessor 's
register CPdest.
The MIPS has a floating point coprocessor (numbered 1) that operates
on single precision (32-bit) and double precision (64-bit) floating
point numbers. This coprocessor has its own registers, which are
numbered $f0-$f31. Because these registers are only
32-bits wide, two of them are required to hold doubles. To simplify
matters, floating point operations only use even-numbered
registers-including instructions that operate on single floats.
Values are moved in or out of these registers a word (32-bits) at a
time by lwc1, swc1, mtc1, and mfc1
instructions described above or by the l.s, l.d, s.s, and s.d pseudoinstructions described below. The flag set
by floating point comparison operations is read by the CPU with its
bc1t and bc1f instructions.
In all instructions below, FRdest, FRsrc1, FRsrc2,
and FRsrc are floating point registers (e.g., $f2).
- abs.d FRdest, FRsrc
- Floating Point Absolute Value Double
-
abs.s FRdest, FRsrc
- Floating Point Absolute Value Single
- Compute the absolute value of the floating float double (single) in
register FRsrc and put it in register FRdest.
- add.d FRdest, FRsrc1, FRsrc2
- Floating Point Addition Double
- add.s FRdest, FRsrc1, FRsrc2
- Floating Point Addition Single
- Compute the sum of the floating float doubles (singles) in registers
FRsrc1 and FRsrc2 and put it in register FRdest.
- c.eq.d FRsrc1, FRsrc2
- Compare Equal Double
- c.eq.s FRsrc1, FRsrc2
- Compare Equal Single
- Compare the floating point double in register FRsrc1 against
the one in FRsrc2 and set the floating point condition flag
true if they are equal.
- c.le.d FRsrc1, FRsrc2
- Compare Less Than Equal Double
- c.le.s FRsrc1, FRsrc2
- Compare Less Than Equal Single
- Compare the floating point double in register FRsrc1 against
the one in FRsrc2 and set the floating point condition flag
true if the first is less than or equal to the second.
- c.lt.d FRsrc1, FRsrc2
- Compare Less Than Double
- c.lt.s FRsrc1, FRsrc2
- Compare Less Than Single
- Compare the floating point double in register FRsrc1 against
the one in FRsrc2 and set the condition flag true if the first
is less than the second.
- cvt.d.s FRdest, FRsrc
- Convert Single to Double
- cvt.d.w FRdest, FRsrc
- Convert Integer to Double
- Convert the single precision floating point number or integer in
register FRsrc to a double precision number and put it in
register FRdest.
- cvt.s.d FRdest, FRsrc
- Convert Double to Single
cvt.s.w FRdest, FRsrc- Convert Integer to Single
- Convert the double precision floating point number or integer in
register FRsrc to a single precision number and put it in
register FRdest.
- cvt.w.d FRdest, FRsrc
- Convert Double to Integer
cvt.w.s FRdest, FRsrc- Convert Single to Integer
- Convert the double or single precision floating point number in
register FRsrc to an integer and put it in register FRdest.
- div.d FRdest, FRsrc1, FRsrc2
- Floating Point Divide Double
- div.s FRdest, FRsrc1, FRsrc2
- Floating Point Divide Single
- Compute the quotient of the floating float doubles (singles) in
registers FRsrc1 and FRsrc2 and put it in register
FRdest.
- l.d FRdest, address
- Load Floating Point Double
- l.s FRdest, address
- Load Floating Point Single
- Load the floating float double (single) at address into register
FRdest.
- mov.d FRdest, FRsrc
- Move Floating Point Double
- mov.s FRdest, FRsrc
- Move Floating Point Single
- Move the floating float double (single) from register FRsrc to
register FRdest.
- mul.d FRdest, FRsrc1, FRsrc2
- Floating Point Multiply Double
- mul.s FRdest, FRsrc1, FRsrc2
- Floating Point Multiply Single
- Compute the product of the floating float doubles (singles) in
registers FRsrc1 and FRsrc2 and put it in register
FRdest.
- neg.d FRdest, FRsrc
- Negate Double
- neg.s FRdest, FRsrc
- Negate Single
- Negate the floating point double (single) in register FRsrc
and put it in register FRdest.
- s.d FRdest, address
- Store Floating Point Double
- s.s FRdest, address
- Store Floating Point Single
- Store the floating float double (single) in register FRdest at
address.
- sub.d FRdest, FRsrc1, FRsrc2
- Floating Point Subtract Double
- sub.s FRdest, FRsrc1, FRsrc2
- Floating Point Subtract Single
- Compute the difference of the floating float doubles (singles) in
registers FRsrc1 and FRsrc2 and put it in register
FRdest.
- rfe
- Return From Exception
- Restore the Status register.
- syscall
- System Call
- Register $v0 contains the number of the system call (see
Table 1) provided by SPIM.
- break n
- Break
- Cause exception . Exception 1 is reserved for the debugger.
- nop
- No operation
- Do nothing.